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GAL20RA10
High-Speed Asynchronous E2CMOS PLD Generic Array LogicTM Features
* HIGH PERFORMANCE E2CMOS (R) TECHNOLOGY -- 7.5 ns Maximum Propagation Delay -- Fmax = 83.3 MHz -- 9 ns Maximum from Clock Input to Data Output -- TTL Compatible 8 mA Outputs -- UltraMOS(R) Advanced CMOS Technology * 50% to 75% REDUCTION IN POWER FROM BIPOLAR -- 75mA Typical Icc * ACTIVE PULL-UPS ON ALL PINS * E CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100 ms) -- 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS -- Independent Programmable Clocks -- Independent Asynchronous Reset and Preset -- Registered or Combinatorial with Polarity -- Full Function and Parametric Compatibility with PAL20RA10 * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- State Machine Control -- Standard Logic Consolidation -- Multiple Clock Logic Designs * ELECTRONIC SIGNATURE FOR IDENTIFICATION
2
Functional Block Diagram
PL
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (80X40)
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
Description
The GAL20RA10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor's E2CMOS circuitry achieves power levels as low as 75mA typical ICC which represents a substantial savings in power when compared to bipolar counterparts. E2 technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20RA10 is a direct parametric compatible CMOS replacement for the PAL20RA10 device. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
OE
Pin Configuration
DIP PLCC
I/O/Q I/O/Q Vcc PL NC
PL I I I
25 I/O/Q I/O/Q
1
24
Vcc I/O/Q I/O/Q
4 I I I NC I I I 11 12 9 7 5
2
28
26
I I I I I I I GND
GAL 20RA10
6 18
I
I
I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q
GAL20RA10 Top View
14 16
23
I/O/Q NC
21
I/O/Q I/O/Q
19 18
I/O/Q
GND
OE
I
I
I/O/Q
I/O/Q
NC
12
13
OE
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20ra10_02
1
Specifications GAL20RA10
GAL20RA10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
7.5 10
Tsu (ns)
3 4
Tco (ns)
9 11
Icc (mA)
100 100 100
Ordering #
GAL20RA10B-7LJ GAL20RA10B-10LP GAL20RA10B-10LJ GAL20RA10B-15LP GAL20RA10B-15LJ GAL20RA10B-20LP GAL20RA10B-20LJ GAL20RA10B-30LP GAL20RA10B-30LJ
Package
28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC
15
7
15
100 100
20
10
20
100 100
30
20
30
100 100
Industrial Grade Specifications
Tpd (ns)
20
Tsu (ns)
10
Tco (ns)
20
Icc (mA)
120 120
Ordering #
GAL20RA10B-20LPI GAL20RA10B-20LJI
Package
24-Pin Plastic DIP 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX X XX
GAL20RA10B Device Name Grade Blank = Commercial I = Industrial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL20RA10
Output Logic Macrocell (OLMC)
The GAL20RA10 OLMC consists of 10 D flip-flops with individual asynchronous programmable reset, preset and clock product terms. The sum of four product terms and an Exclusive-OR provide a programmable polarity D-input to each flip-flop. An output enable term combined with the dedicated output enable pin provides tri-state control of each output. Each OLMC has a flip-flop bypass, allowing any combination of registered or combinatorial outputs. The GAL20RA10 has 10 dedicated input pins and 10 programmable I/O pins, which can be either inputs, outputs, or dynamic I/ O. Each pin has a unique path to the logic array. All macrocells have the same type and number of data and control product terms, allowing the user to exchange I/O pin assignments without restriction.
Asynchronous Reset and Preset
Each GAL20RA10 macrocell has an independent asynchronous reset and preset control product term. The reset and preset product terms are level sensitive, and will hold the flip-flop in the reset or preset state while the product term is active independent of the clock or D-inputs. It should be noted that the reset and preset term alter the state of the flip-flop whose output is inverted by the output buffer. A reset of the flip-flop will result in the output pin becoming a logic high and a preset will result in a logic low. RESET PRESET FUNCTION 0 0 Registered function of data product term 1 0 Reset register to "0" (device pin = "1") 0 1 Preset register to "1" (device pin = "0") 1 1 Register-bypass (combinatorial output)
Independent Programmable Clocks
An independent clock control product term is provided for each GAL20RA10 macrocell. Data is clocked into the flip-flop on the active edge of the clock product term. The use of individual clock control product terms allow up to ten separate clocks. These clocks can be derived from any pin or combination of pins and/or feedback from other flip-flops. Multiple clock sources allow a number of asynchronous register functions to be combined into a single GAL20RA10. This allows the designer to combine discrete logic functions into a single device.
Combinatorial Control
The register in each GAL20RA10 macrocell may be bypassed by asserting both the reset and preset product terms. While both product terms are active the flip-flop is bypassed and the D- input is presented directly to the inverting output buffer. This provides the designer the ability to dynamically configure any macrocell as a combinatorial output, or to fix the macrocell as combinatorial only by forcing both reset and preset product terms active. Some logic compilers will configure macrocells as registered or combinatorial based on the logic equations, others require the designer to force the reset and preset product terms active for combinatorial macrocells.
Programmable Polarity
The polarity of the D-input to each macrocell flip-flop is individually programmable to be active high or low. This is accomplished with a programmable Exclusive-OR gate on the D-input of each flipflop. The polarity of the pin is active low when XOR bit is programmed (or zero) and is active high when XOR bit is erased (or one). Because of the inverted output buffer, the XOR gate output node is opposite polarity from the pin. It should be noted that the programmable polarity only affects the data latched into the flip-flop on the active edge of the clock product term. The reset, preset and preload will alter the state of the flip-flop independent of the state of programmable polarity bit. The ability to program the active polarity of the D-inputs can be used to reduce the total number of product terms used, by allowing the DeMorganization of the logic functions. This logic reduction is accomplished by the logic compiler, and does not require the designer to define the polarity.
Parallel Flip-Flop Preload
The flip-flops of a GAL20RA10 can be reset or preset from the I/O pins by applying a logic low to the preload pin (pin 1 on DIP package / pin 2 on PLCC package) and applying the desired logic level to each I/O pin. The I/O pins must remain valid for the preload setup and hold time. All 10 flip-flops are reset or preset during preload, independent of all other OLMC inputs. A logic low on an I/O pin during preload will preset the flip-flop, a logic high will reset the flip-flop. The output of any flip-flop to be preloaded must be disabled. Enabling the output during preload will maintain the current logic state. It should be noted that the preload alters the state of the flip-flop whose output is inverted by the output buffer. A reset of the flip-flop will result in the output pin becoming a logic high and a preset will result in a logic low. Note that the common output enable pin will disable all 10 outputs of the GAL20RA10 when held high.
Output Enable
The output of each GAL20RA10 macrocell is controlled by the "AND'ing" of an independent output enable product term and a common active low output enable pin (pin 13 on DIP package / pin 16 on PLCC package). The output is enabled while the output enable product term is active and the output enable pin is low. This output control structure allows several output enable alternatives.
3
Specifications GAL20RA10
Output Logic Macrocell Diagram
PL OE
AR PL D AP XOR (n) PD Q 0 1
Output Logic Macrocell Configuration (Registered With Polarity)
PL OE
PL D
AR PD Q AP
XOR (n)
Output Logic Macrocell Configuration (Combinatorial With Polarity)
OE
XOR (n)
4
Specifications GAL20RA10
GAL20RA10 Logic Diagram
DIP (PLCC) Package Pinouts
1 (2)
0 0 4 8 12 16 20 24 28 32 36
PL
OLMC
280
23 (27)
2 (3)
320
XOR - 3200
OLMC
600
22 (26)
3 (4)
640
XOR - 3201
OLMC
920
21 (25)
4 (5)
960
XOR - 3202
OLMC
1240
20 (24)
5 (6)
1280
XOR - 3203
OLMC
1560
19 (23)
6 (7)
1600
XOR - 3204
OLMC
1880
18 (21)
7 (9)
1920
XOR - 3205
OLMC
2200
17 (20)
8 (10)
2240
XOR - 3206
OLMC
2520
16 (19)
9 (11)
2560
XOR - 3207
OLMC
2840
15 (18)
10 (12)
2880
XOR - 3208
OLMC
3160
14 (17)
11 (13)
XOR - 3209
13 (16)
OE
64-USER ELECTRONIC SIGNATURE FUSES 3210, 3211, .... .... 3272, 3273 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
5
Specifications GAL20RA10B
Absolute Maximum Ratings(1)
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied .......... -2.5 to VCC +1.0V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ..........................-40 to +85C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.3 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 10 0.5 -- 8 -3.2 -135
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -50
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -7/-10/-15/-20/-30
--
75
100
mA
INDUSTRIAL ICC Operating Power
Supply Current
VIL = 0.5V
VIH = 3.0V
L -20
--
75
120
mA
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
6
Specifications GAL20RA10B
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAM. TEST COND1. COM COM COM / IND COM
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low I or I/O to Output Enabled / Disabled OE to Output Enabled / Disabled Input or I/O to Async. Reset / Preset Async. Reset / Preset Pulse Duration Async. Reset / Preset Recovery Time Preload Pulse Duration Preload Setup Time Preload Hold Time 2 2 3 2
-7
MIN.
-10
MAX. MIN.
-15
-20
-30 UNITS
MAX.
MAX. MIN.
MAX. MIN.
MAX. MIN.
tpd tco tsu th fmax3
A A -- -- A A
7.5 9 -- -- -- -- -- -- 7.5 5 9 -- -- -- -- --
2 2 4 3 66.7 71.4 7 7 -- -- -- 10 7 10 7 7
10 11 -- -- -- -- -- -- 10 9 11 -- -- -- -- --
-- -- 7 3 45.0 50.0 10 10 -- -- -- 15 10 15 10 10
15 15 -- -- -- -- -- -- 15 12 15 -- -- -- -- --
-- -- 10 3 33.3 41.7 12 12 -- -- -- 20 12 20 15 15
20 20 -- -- -- -- -- -- 20 15 20 -- -- -- -- --
-- -- 20 10 20.0 25.0 20 20 -- -- -- 20 20 30 25 25
30 30 -- -- -- -- -- -- 30 20 30 -- -- -- -- --
ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns
83.3 83.3 6 6 -- -- -- 6 7 8 5 5
twh twl ten/tdis ten/tdis tar/tap tarw/tapw tarr/tapr twp tsp thp
-- -- B,C B,C A -- -- -- -- --
1) Refer to Switching Test Conditions section. 2) Refer to fmax Descriptions section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 10 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications GAL20RA10
Switching Waveforms
INPUT or I/O FEEDBACK VALID INPUT INPUT or I/O FEEDBACK VALID INPUT
tpd
COMBINATORIAL OUTPUT CLK
tsu
VALID CLOCK
th
VALID CLOCK
tco
REGISTERED OUTPUT
Combinatorial Output
INPUT or I/O FEEDBACK
Registered Output
tdis
OUTPUT
ten
INPUT or I/O FEEDBACK
VALID INPUT
tar
Q-OUTPUT OF REGISTER
Input or I/O to Output Enable/Disable
twh
CLK
twl
REGISTERED OUTPUT PIN
tap
Clock Width
twp
PL
Q-OUTPUT OF REGISTER
REGISTERED OUTPUT PIN
tsp
ALL I/O PINS
thp
Asynchronous Reset and Preset
INPUT or I/O FEEDBACK DRIVING AP or AR CLK
VALID INPUT
Parallel Preload
tapw/arw
tapr/arr
OE
Asynchronous Reset and Preset Recovery
tdis
OUTPUT
ten
OE to Enable / Disable
8
Specifications GAL20RA10
fmax Descriptions
CLK
CLK
LOGIC ARRAY
REGISTER
LOGIC ARRAY
REGISTER
tsu
tco
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times -7/-10 -15/-20/-30 GND to 3.0V 2ns 10% - 90% 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
Input Timing Reference Levels Output Timing Reference Levels Output Load
3-state levels are measured 0.5V from steady-state active level.
R2
C L*
Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 470 470 470 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
9
Specifications GAL20RA10
Electronic Signature
An electronic signature word is provided in every GAL20RA10 device. It contains 64 bits of reprogrammable memory that contains user defined data. Some uses include user ID codes, revision numbers, pattern identification or inventory control codes. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature bits if programmed to any value other then zero(0) will alter the checksum of the device.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
Input Buffers
GAL20RA10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance and present a much lighter load to the driving logic than traditional bipolar devices. GAL20RA10 input buffers have active pull-ups within their input structure. As a result, unused inputs and I/Os will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce Icc for the device. Typical Input Pull-up Characteristic
I n p u t C u r r e n t (u A )
0
Security Cell
A security cell is provided in every GAL20RA10 device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once this cell is programmed. The Electronic Signature is always available regardless of the security cell state.
Latch-Up Protection
GAL20RA10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
-20
-40 -60 0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
10
Specifications GAL20RA10
Power-Up Reset
Vcc (min.)
Vcc
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
Circuitry within the GAL20RA10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be high on power-up, because of the inverting buffer on the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown to the right. Because of the asynchronous
nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20RA10. First, the Vcc rise must be monotonic. Second, the clock input must be at a static TTL level as shown in the diagram during power up. The registers will reset within a maximum of 1s. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
(Vref Typical = 3.2V)
Active Pull-up Circuit
Active Pull-up Circuit Tri-State Control Vcc
(Vref Typical = 3.2V)
Vref
Vcc
ESD Protection Circuit
Vref
Vcc
Data Output
PIN
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Input
Typical Output
11
Specifications GAL20RA10
GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.4
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
1.1
1.2
1
1
1
0.9
0.9
0.8
0.8 4.50
4.75
5.00
5.25
5.50
0.8 4.50
4.75
5.00
5.25
5.50
0.6 4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.6
Normalized Tsu vs Temp
Normalized Tpd
1.2 1.1 1 0.9 0.8 0.7
0 -55 -25 25 50 75 100 125
Normalized Tco
1.2 1.1 1 0.9 0.8 0.7
0 -55 -25 25 50 75 100 125
Normalized Tsu
1.4 1.2 1 0.8 0.6
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
Delta Tco (ns)
1 2 3 4 5 6 7 8 9 10
-0.5 -1 -1.5 -2 1 2 3 4 5 6 7 8 9 10
-0.5
-1
-1.5
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
8 8
Delta Tco vs Output Loading
Delta Tpd (ns)
Delta Tco (ns)
6 4 2 0 -2 -4 0
RISE FALL
6 4 2 0 -2 -4 0
RISE FALL
50
100
150
50
100
150
Output Loading (pF)
Output Loading (pF)
12
Specifications GAL20RA10
GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Vol vs Iol
1 0.8 5 4
Voh vs Ioh
4
Voh vs Ioh
3.75
Voh (V)
0.6 0.4 0.2 0 0 10 20 30 40
3 2 1 0 0 10 20 30 40 50 60 70 80
Voh (V)
Vol (V)
3.5
3.25
3 0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.2 1.3
Normalized Icc vs Temp
1.40
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.1
1.1 1 0.9 0.8 0.7
-55 -25 0 25 75 100 125
Normalized Icc
1.2
1.30 1.20 1.10 1.00 0.90 0.80 0 25 50 75
1
0.9
0.8 4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10
Input Clamp (Vik)
0 10 20
Delta Icc (mA)
8 6 4 2 0 0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70
Iik (mA)
30 40 50 60 70 80 90 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
13
Specifications GAL20RA10
GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.1
Normalized Tco vs Vcc
1.6 RISE 1.05 FALL
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L
1.1
1.4 1.2 1 0.8 0.6 0.4 4.50
PT L->H
1
1
0.9
0.95
0.8 4.50
4.75
5.00
5.25
5.50
0.9 4.50
4.75
5.00
5.25
5.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
1.2 1.1 1 0.9 0.8 0.7
1.2 1.1 1 0.9 0.8 0.7
Normalized Tsu
PT H->L PT L->H
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7 0.6
-55 -25 0 25 50 75 90 125
0
-55
-25
-55
-25
25
50
75
90
0
25
50
75
125
90
Temperature (deg. C)
Temperature (deg. C)
125
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
-0.2 -0.4 -0.6 -0.8 -1 -1.2 1 2 3 4 5 6 7 8 9 10
Delta Tco (ns)
-0.2 -0.4 -0.6 -0.8 -1 -1.2 1 2 3 4 5 6 7 8 9 10
RISE FALL
RISE FALL
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 8 6 4 2 0 -2 -4 0 50 100 150 200 250 300
Delta Tco vs Output Loading
14 12 10 8 6 4 2 0 -2 -4 0 50
Delta Tpd (ns)
FALL
Delta Tco (ns)
RISE
RISE FALL
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
14
Specifications GAL20RA10
GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
3.75
Voh vs Ioh
3.625
Voh (V)
3 2 1 0 0.00
1.5 1 0.5 0 0.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
3.5
3.375
20.00
40.00
60.00
80.00
3.25 0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.40
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.10
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.30 1.20 1.10 1.00 0.90 0.80 0 25 50 75
1.00
1
0.90
0.9
0.80 4.50
0.8 4.75 5.00 5.25 5.50
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
5
Input Clamp (Vik)
0 10 20
Delta Icc (mA)
4 3 2 1 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Iik (mA)
30 40 50 60 70 80 90 -2.00 -1.00 0.00
Vin (V)
Vik (V)
15

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